Power must be supplied to the large number of electrical components fabricated in an integrated circuit. Typically this is done by routing one or more conductive layers throughout the circuit, and making contact through previously deposited layers to the components constructed below. One disadvantage of the prior art method of powering integrated circuits is that the deposited and etched conducting layers require extra processing steps. Extra processing steps means extra expense and an increased potential for processing errors and defects.
A second disadvantage of the commonly used power routing schemes is the consumption of significant portions of the semiconductor chip surface that otherwise could be used for active circuit fabrication. Because the circuit powering conductive layers must periodically make contact through previously deposited layers, any mask alignment errors create the potential for a missed or insufficient contact between the conductive layer and the circuit component to be powered. Also, many typically used conducting materials are poor at filling small high aspect ratio contact holes. To account for these processing tolerances and undesirable material properties, chip designers have been forced to design larger dimension contacts than necessary in principle for proper circuit performance. This is particularly disadvantageous in the design and manufacture of semiconductor memories, where the fabrication cost per bit is optimized with the smallest possible size cell that assures low sensitivity to process instabilities.
The CMOS bulk 6-T SRAM cell is just one example where traditional integrated circuit powering techniques have added significantly to the cost of fabrication. The bulk 6-T cell is superior in performance to the commonly used NMOS 4-T SRAM cell, by virtue of its better data retention, lower power consumption and faster switching speed. The bulk 6-T cell is also superior to the stacked CMOS thin-film-transistor (TFT) 6-T SRAM cell, which is subject to a number of process sensitivities and impurity problems because of the silicon deposit and recrystallization fabrication steps. Nevertheless, the large size and associated high fabrication cost of the bulk 6-T SRAM cell means it is not as frequently used as the 4-T and TFT SRAM cells.